Methods for bi-directional signaling

ABSTRACT

Improved methods and apparatuses are provided for conducting bi-directional signaling and testing. The outputs of at least two driver circuits are connected to a resistive network. The output signals from the driver circuits are combined through the resistive network to produce a resultant signal that is an attenuated version of at least one of the output signals. The resistive network and the driver circuits are configured such that the resultant signal is provided to an output node of the resistive network but not to an input node of the resistive network. An input/output node of an external circuit is connected to the input node of the resistive network, wherein the external circuit is configured to receive the resultant signal and output an external signal. An input node of a receiver circuit is connected to the output node of the resistive network. The resultant signal is then simultaneously provided to the external circuit and the external signal to the receiver circuit, bi-directionally through the resistive network.

TECHNICAL FIELD

[0001] This invention relates to bi-directional signaling, and moreparticularly to improved methods and apparatuses for conducting andtesting bi-directional signaling over a single transmission line.

BACKGROUND

[0002] In a typical integrated circuit testing configuration, testsignals only travel in one direction at a given time between the testerand the integrated circuit. Such uni-directional signaling works wellfor integrated circuits with dedicated input or output pads/pins.However, many integrated circuits are configured with input/output (I/O)circuits that support bi-directional signaling through the same pad/pin.For example, certain memory integrated circuits include I/O circuitsthrough which access is provided to the memory. As such, data can bewritten to the memory by providing (inputting) applicable signals to apad/pin of an I/O circuit. The same pad/pin of the I/O circuit can beused to read data from the memory when the I/O circuit provides(outputs) a representative signal to the pad/pin. In certainimplementations, the inputting and outputting of signals associated withthe memory occur simultaneously.

[0003] Fully testing the operation of such integrated circuits can bedifficult if not impossible, as the uni-directional tester will need tooperatively switch the signaling direction back and forth betweensending test signals to the integrated circuit and receiving testsignals from the integrated circuit.

[0004] By way of example, FIG. 1 depicts a conventional uni-directionalsignaling testing arrangement 100 configured to support limitedbi-directional signaling. Arrangement 100, in this example, includes atester device 102 operatively coupled through a single transmission line104 to a device under test (DUT) 106 (e.g., an integrated circuit).Here, to conduct limited bi-directional signaling over transmission line104, tester device 102 and DUT 106 need to take turns insending/receiving signals. Hence, this is essentially a time-multiplexedsolution for conducting and testing bi-directional signaling.

[0005] As mentioned above, one of the drawbacks to testing arrangement100 is that it is unable to conduct simultaneous bi-directionalsignaling. As such, DUT 106 may not be fully tested since only a portionof the operational I/O bandwidth can be tested. More specifically, theaverage bandwidth of transmission line 104 will be lower, because thereis usually a need to pause between switching the direction of thesignaling to allow the voltage in transmission line 104 to dissipate.

[0006] Hence, there is a need for arrangements that allow the fulloperational bandwidth to be tested.

[0007] As a basic reference, FIG. 2 depicts an exemplary receiverportion 120 of tester device 102. Here, receiver portion 120 includes ahigh gain comparator 122 that is configured to measure if the receivedsignal from DUT 106 is above or below a threshold voltage level(V_(CMP)). Comparator 122 outputs the measured voltage level (V_(RCV)).Receiving circuits such as this and associated signal driving circuitsare well known.

[0008] With this in mind, FIGS. 3a-b depict two common time-multiplexedtesting arrangements and techniques. As shown in the example of FIG. 3a,tester device 102 includes a receiver portion represented by comparator122, and a driver portion represented by operational amplifier 124.These portions are operatively configured to time-share transmissionline 104. Here, since both the receiver and driver portions utilize thesame transmission line 104, there is a need to pause transmissions whenswitching to allow earlier signals to propagate.

[0009]FIG. 3b depicts a slightly improved testing arrangement, whereindual transmission lines are provided. Here, transmission line 104 a isconfigured to carry signals from operational amplifier 124to DUT 106;transmission line 104 b is configured to carry signals from DUT 106 tocomparator 122. Because of the separate transmission lines, there is noneed to wait as long for propagation delays when switching betweenreceiver and driver portions. While this reduces the turn around timedelays, the performance of the DUT cannot be fully tested, because thetransmission sequence still needs to be reversed (i.e. simultaneousbi-directional signaling is not supported).

[0010] There are some test circuits that allow for simultaneousbi-directional signaling. However, such circuits are configured for usewith specific devices, such as telephone devices. By way of example,FIG. 4 depicts an exemplary arrangement for providing bi-directionalsignaling over two transmission lines 126. As shown, this arrangementincludes similarly configured transceivers (identified as Transceiver Aand Transceiver B) coupled together through transmission lines 126.Since this arrangement is common to telephony, the transmission linesare usually implemented using twisted pair wires. Although detailedanalysis of this well known arrangement is beyond the scope of thisdocument, a brief conceptual description is provided below. Readersseeking additional information are directed, for example, to a text byWilliam J. Dally and John W. Poulton, Digital Systems Engineering,Section 8.3, published by Cambridge University Press, Mar. 1998.

[0011] Conceptually, the arrangement in FIG. 4 is fairly simple inoperation in that each transceiver is configured to subtract itsoutgoing signal from the incoming signal before sampling the data. Here,for example, in Transceiver A forward voltage V_(fl) (which includestransmitted data D_(TA)) is subtracted from received voltage V_(LA)using a comparator to produce received data D_(RA). Note, that bothtransceivers require V_(L(A,B)) and V_(T) (a threshold voltage) ascarried through transmission lines 126.

[0012] Ensuring that a DUT having only has a single I/O pad/pin workscorrectly is less straightforward. The pin electronics in mostconventional semiconductor testing equipment (e.g., automated testingequipment (ATE)) can only be configured to receive or transmit data at agiven time, because the test equipment receiver lacks the secondexternally accessible port used to cancel any outgoing signal that isapplied to the DUT (i.e., as in the exemplary arrangement in FIG. 4). Assuch, the standard configurations for testing I/O connections are unableto test simultaneous I/O because the tester driver will interfere withdata seen at the tester receiver. One possible solution to this problemwould be to redesign the tester. This would likely be a very expensiveengineering endeavor, since testers tend to be very precise andcarefully engineered devices; for example, an average semiconductor ATEdevice can cost in excess of one million dollars.

[0013] Consequently, there is a need for improved methods andapparatuses for conducting bi-directional signaling and testing devicesthat support such bi-directional signaling.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete understanding of the various methods andapparatuses of the present invention may be had by reference to thefollowing detailed description when taken in conjunction with theaccompanying drawings wherein:

[0015]FIG. 1 is a block diagram depicting an exemplary conventionalsignal testing arrangement having a tester device coupled through atransmission line to a device under test (DUT).

[0016]FIG. 2 is a schematic diagram depicting a portion of an exemplaryprior art receiver circuit with a testing device as in FIG. 1.

[0017]FIGS. 3a-b are partial schematic diagrams depicting two differentprior art circuits and techniques for testing non-simultaneousbi-directional signaling using time-multiplexed test signals.

[0018]FIG. 4 is a partial schematic diagram depicting a prior artcircuit and technique for simultaneously sending bi-directional signalsusing two transmission lines.

[0019]FIG. 5 is a schematic diagram depicting a novel circuit andtechnique for simultaneously sending and receiving bi-directionalsignals over a single transmission line to an I/O circuit in a DUT, inaccordance with certain exemplary implementations of the presentinvention.

[0020]FIG. 6 is a time-line graph associated with the exemplary circuitof FIG. 5, which depicts selected voltages resulting from a signaloutput from the device under test (DUT).

[0021]FIG. 7 is a time-line graph associated with the exemplary circuitof FIG. 5, which depicts selected voltages resulting from signals outputfrom the tester device's test driver circuits.

DETAILED DESCRIPTION

[0022] Tester devices, such as ATEs, tend to come with a plurality ofdrivers and receivers. Referring back to FIG. 1, the end user of ageneral-purpose tester device 102 typically couples the DUT 106 to thetester device 102 through an intervening load board (not shown) thatprovides the necessary circuitry to complete the transmission line 104.It is here, for example, in the load board, or other configuredinterconnecting circuitry, that the methods and apparatuses, inaccordance with the present invention, are implementable. One possiblearrangement is depicted in the exemplary implementation of FIG. 5. Thoseskilled in the art will further recognize that this and similarcircuitry may also be incorporated into the tester device 102 itself.Moreover, the techniques taught herein may be applied to other non-testrelated bi-directional communicating circuits/devices. For example, thetechniques may be used whenever it is necessary to interfacenon-simultaneous I/O circuits (e.g., dedicated drivers and receivers)with simultaneous bi-directional circuits (e.g., I/O circuits of anintegrated circuits).

[0023] With reference to FIG. 5, an arrangement 300 is depicted forconducting and testing bi-directional signaling with a targeted device,in this example, DUT 106. In addition to DUT 106, arrangement 300includes a tester receiver 302, two tester drivers 304 and 306, and aninterconnecting arrangement of transmission lines and a matchingresistor network consisting of resistors R₁, R₂ and R₃ (308, 310 and312, respectively). Given this configuration, any signal that testerdriver 304 outputs will be received at identified nodes C and D, butwill be attenuated at node C due to resistor R₁ 308. Similarly, anysignal that is output by tester driver 306 will also be received atnodes C and D, but will be attenuated more at node D due to resistor R₁308.

[0024] By varying the output level and subsequent attenuation of theopposing or differential signals from tester drivers 304 and 306, asreceived at DUT 106 (node D) and tester receiver 302 (node C), it ispossible to send a non-zero signal to DUT 106 and at the same time senda substantially negligible signal to tester receiver 302 (node C).

[0025] Preferably, the signal output by tester driver 306 reduces theopposing signal output by tester driver 304 at tester receiver 302 (nodeC) to the point where the signal from tester driver 306 is effectivelycancelled or rendered negligible. This allows signals output by DUT 106to be received by tester receiver 302 without interference from thedrivers 304 and 306. The signal (V_(A)) output by tester driver 304 willbe strong enough to be received by DUT 106 (node D) despite beingreduced slightly by the opposing signal (V_(B)) output by tester driver306.

[0026] In other words, the combination of the signals from testerdrivers 304 and 306 resulting from the resistor network, at the DUT 106(node D), is going to be a signal of appropriate magnitude and othercharacteristics such that it mimics or otherwise matches what would beseen from a dedicated driver circuit normally used to test an input pinof DUT 106. With respect to tester receiver 302 (node C), the resistornetwork combines the signals from tester drivers 304 and 306 in a mannersuch that the resultant signal at node C is at a magnitude that isessentially negligible (e.g., within a noise level) to tester receiver302 and does not, therefore, interfere with other signals received atnode C, for example, as output by DUT 106. Note also that the signalfrom DUT 106 is presented with matched impedance by the resistor networksuch that reflections are not sent back along the transmission line.

[0027] In a particular example, tester driver 304 provides the testdrive signal that is represented in the resultant signal as applied toDUT 106 (node D); conversely, tester driver 306 provides a cancel signalthat, when combined through the resistor network, causes most if not allof the drive signal from tester driver 304 to be attenuated at node C.

[0028] In accordance with certain exemplary implementations, theresistive network (or another like combining circuit) is included in aload board 313 as represented by the dashed line box. Load board 313 mayalso include one or more transmission lines and related connectorsincluding one or more connectors or sockets for receiving the DUT.

[0029] As illustratively depicted in exemplary arrangement 300, thetransmission lines between tester receiver 302, tester drivers 304 and306, and DUT 106 have the same impedance (Z₀). Consequently, toeliminate reflections tester receiver 302, tester drivers 304 and 306,and DUT 106 include impedance matching resistors (R₀), which matchimpedance (Z₀). Similarly, matching resistor R₁ (308) is configured tomatch impedance (Z₀). There are a plurality of values that can beapplied to resistors R₂ and R₃ (310 and 312, respectively), based on thedriver signal voltages V_(A) and V_(B). By way of example, in certainimplementations, the following values were used:

[0030] R₁=Z₀, R₂=R₃=1.4142*Z₀, V_(A)=5.83 V, and V_(B)=−0.4142* V_(A).

[0031] Here, for example, the resistive values of R₂ and R₃ can beselected based on two criteria. First, the values are selected such thata selected driver signal voltage V_(B) will substantially cancel outdriver signal voltage V_(A) at node C. Secondly, the values are selectedsuch that at least an appropriate amount of driver signal voltage V_(A)is present at node D.

[0032]FIG. 6 is a time-line graph associated with a SPICE simulation ofexemplary arrangement 300, which depicts selected voltage levelsresulting from a signal output from DUT 106. Here, the data transmissionrepresented by line 400, begins in DUT 106 at about 1 nS with a voltageof about 1 V. This voltage is reduced by about 50% at node D, asdepicted by line 402. In this example, this initial attenuation is dueto source termination within the output driver of the DUT 106. After aslight propagation delay, the signal, attenuated by another 50%(resulting in about 0.25 V as represented by line 404) is received atnode C in the tester receiver. As illustrated, essentially none of thesignal energy is reflected back to DUT 106 from the matching networkbecause the resistive network is configured to impedance match thetransmission line between DUT 106 and the resistive network.

[0033]FIG. 7 is also time-line graph associated with a SPICE simulationof exemplary arrangement 300, which depicts selected voltage levelsresulting from signals output from tester driver 304 and tester driver306. Here, tester driver 304 and tester driver 306 are configured tobegin outputting their respective opposing signals at about 1 nS. Line408 represents the voltage at node A, as output by tester driver 304.Line 410 represents the voltage at node B, as output by tester driver306. Line 412 represents the voltage received at DUT 106 (node D). Here,the resulting received voltage at DUT 106 (at about 3 nS) isapproximately 1.0 V as a result of the combined driver voltages(represented by lines 408 and 410) wherein the drive signal (408) isattenuated in the resistive network by the opposing cancel signal (410).Furthermore, line 414, which as shown is substantially steady at aboutzero volts, represents the voltage received at tester receiver 302 (nodeC) due to the combination of the drive and cancel signals output fromtester drivers 304 and 306, respectively. Note that there may be someslight reflection back to the tester drivers.

[0034] Therefore, as shown in FIG. 7, a resultant signal derived fromthe signals from tester drivers 304 and 306 will be received by DUT 106but not significantly seen at the input to comparator 122 in testerreceiver 302. As shown in FIG. 6, simultaneously transmitted signalsfrom DUT 106 will be received at comparator 122. Thus, arrangement 300supports simultaneous bi-directional signaling and related testing.

[0035] Although some preferred implementations of the various methodsand apparatuses of the present invention have been illustrated in theaccompanying Drawings and described in the foregoing DetailedDescription, it will be understood that the invention is not limited tothe exemplary implementations disclosed, but is capable of numerousrearrangements, modifications and substitutions without departing fromthe spirit of the invention as set forth and defined by the followingclaims.

What is claimed is:
 1. A method comprising: connecting the output of atleast two driver circuits to a resistive network, wherein the outputsignals from the at least two driver circuits are combined through theresistive network to produce a resultant signal; and configuring theresistive network and the at least two driver circuits such that theresultant signal is provided to a first node of the resistive networkbut not to a second node of the resistive network.
 2. The method asrecited in claim 1, wherein the resultant signal includes an attenuatedversion of at least one of the output signals.
 3. The method as recitedin claim 1, further comprising: coupling an input/output node of anexternal circuit to the first node of the resistive network, theexternal circuit being configured to receive the resultant signal andoutput an external signal; and coupling an input node of a receivercircuit to the second node of the resistive network.
 4. The method asrecited in claim 3, further comprising: simultaneously providing theresultant signal to the external circuit and the external signal to thereceiver circuit, bi-directionally through a connector coupling theresistive network to the external circuit.
 5. The method as recited inclaim 4, wherein the external circuit includes a device under test(DUT).
 6. The method as recited in claim 5, wherein the device undertest (DUT) includes an integrated circuit.
 7. The method as recited inclaim 4, wherein the at least two driver circuits and the receivercircuit are part of an automated test equipment (ATE) device.
 8. Themethod as recited in claim 7, wherein the resistive network is part ofthe automated test equipment (ATE) device.
 9. The method as recited inclaim 7, wherein the resistive network is included in a load boardcoupled to the external circuit and the automated test equipment (ATE)device.
 10. An apparatus comprising: a receiver circuit configured toreceive an external signal; a first driver circuit configured to outputa first signal; a second driver circuit configured to output a secondsignal; and a resistive circuit coupling the receiver circuit, firstdriver circuit and second driver circuit together, the resistive circuitbeing configured to combine the first signal and the second signal toproduce a resultant signal at a first node and a substantiallyattenuated signal at a second node to which the receiver circuit iscoupled, and wherein the attenuated signal has an amplitude within anegligible range with respect to operation of the receiver circuit. 11.The apparatus as recited in claim 10, wherein the resistive circuitincluding a first resistive element, a second resistive element and athird resistive element, and wherein a first transmission path includingthe second resistive element is coupled to the output of the firstdriver circuit and a first node of the first resistive element, a secondtransmission path including the third resistive element is coupled tothe output of the second driver circuit and a second node of the firstresistive element, the second node of the first resistive element isfurther coupled to an input node of the receiver circuit, and the firstnode of the first resistive element is further configurable to receivethe external signal.
 12. The apparatus as recited in claim 11, whereinone of the first and second signals has a positive voltage level, andwherein another of the first and second signals has a negative voltagelevel.
 13. The apparatus as recited in claim 11, wherein at least one ofthe first, second and third resistive elements is a resistor.
 14. Theapparatus as recited in claim 11, wherein the first and secondtransmission paths further include first and second transmission lines,respectively, and the receiver circuit is coupled to the second node ofthe first resistive element through a third transmission line.
 15. Theapparatus as recited in claim 14, wherein each of the first, second andthird transmission lines present substantially the same impedance. 16.The apparatus as recited in claim 14, further comprising a fourthtransmission line having one end coupled to the first node of the firstresistive element and an other end configurable to receive the externalsignal.
 17. The apparatus as recited in claim 16, wherein each of thefirst, second, third, and fourth transmission lines presentsubstantially the same impedance.
 18. The apparatus as recited in claim16, wherein the first resistive element is matched to the impedance aspresented by the fourth transmission line.
 19. The apparatus as recitedin claim 14, wherein the receiver circuit is impedance matched to thethird transmission line, first driver circuit is impedance matched tothe first transmission line, and second driver circuit is impedancematched to the second transmission line.
 20. The apparatus as recited inclaim 10, wherein the resultant signal at the first node is provided toa device under test (DUT) that is coupled to the first node, the DUTbeing configured to further provide the external signal to the receivercircuit.
 21. The apparatus as recited in claim 20, wherein the externalsignal experiences a generally matched impedance path when provided tothe receiver circuit from the DUT.
 22. The apparatus as recited in claim10, wherein the receiver circuit, first driver circuit and second drivercircuit are provided within an automated test equipment (ATE) device.23. The apparatus as recited in claim 10, wherein the resistive circuitis provided within a load board.
 24. A system comprising: a deviceconfigured to simultaneously output an external signal and input aresultant signal; a receiver circuit configured to receive the externalsignal; a first driver circuit configured to output a first signal; asecond driver circuit configured to output a second signal; and aresistive circuit coupling the receiver circuit, first driver circuitand second driver circuit together, the resistive circuit beingconfigured to combine the first signal and the second signal to producea resultant signal at a first node and a substantially attenuated signalat a second node to which the receiver circuit is coupled, and whereinthe attenuated signal has an amplitude within a negligible range withrespect to operation of the receiver circuit.
 25. A system comprising: adevice under test (DUT) that is configured to simultaneously output anexternal signal and input a resultant signal; a test apparatusconfigured to test the ability to of the DUT to support simultaneousbi-directional communication, the test apparatus comprising: a receivercircuit configured to receive the external signal; a first drivercircuit configured to output a first signal; a second driver circuitconfigured to output a second signal; and a resistive circuit coupled tothe receiver circuit, the first driver circuit, the second drivercircuit, and the DUT, the resistive circuit being configured to combinethe first signal and the second signal to produce the resultant signalat a first node and a substantially attenuated signal at a second nodeto which the receiver circuit is coupled, and wherein the attenuatedsignal has an amplitude within a negligible range with respect tooperation of the receiver circuit.
 26. A load board apparatus for use incoupling a device under test (DUT) to an automated test equipment (ATE)device, the ATE device having at least two driver circuits and at leastone receiver circuit, the load board apparatus comprising: a combiningcircuit configurable to support bi-directional signaling between the DUTand the ATE device, wherein the combining circuit is configured toreceive a first signal from a first driver circuit and a second signalfrom a second driver circuit, produce a resultant signal based on thefirst and second signals, and apply the resultant signal to the DUT anda substantially attenuated signal to the receiver circuit, wherein thesubstantially attenuated signal has an amplitude within a negligiblerange with respect to operation of the at least one receiver circuit.27. A load board apparatus for use in coupling a device under test (DUT)to an automated test equipment (ATE) device, the ATE device having afirst driver circuit, a second driver circuit and a receiver circuit,the load board apparatus comprising: an output configurable to connectto the receiver circuit of the ATE; a first input configurable toconnect to the first driver circuit of the ATE; a second inputconfigurable to connect to the second driver circuit of the ATE; aconnector configurable to connect to the DUT; and a resistive circuitcoupled to the output, the first input, the second input, and theconnector, the resistive circuit configured to receive a first inputsignal from the first input and a second input signal from the secondinput, the resistive circuit to generate a resultant signal based on thefirst input signal and the second input signal, and provide theresultant signal to the connector, and wherein in generating theresultant signal the resistive circuit causes only a substantiallyattenuated signal to be provided to the output configurable to connectto the receiver circuit of the ATE device, wherein the attenuated signalhas an amplitude within a negligible range with respect to operation ofthe receiver circuit.